Frequency divider works only for some divisors (Verilog on Lattice iCEstick FPGA)

I'm trying to build a frequency divider on a Lattice iCEstick using Verilog (with yosys, arachne-pnr, and icepack/iceprog):

 module demo(input clk, output LED1, LED2, LED3, LED4, LED5);     assign LED1 = state;     // Generate impulse at lower frequency:                                                                                                                              wire out_clk;    reg [31:0] cnt;    initial cnt <= 0;    always @(posedge clk) cnt <= cnt >= 6000000 ? 0 : cnt + 1;    assign out_clk = cnt == 0;     // On impulse, toggle state:                                                                                                                                         reg state;    initial state <= 0;    always @(posedge out_clk) state <= ~state;  endmodule 

This works as expected, i.e. the LED on the board blinks about once a second (the clock is 12MHz).

However, when 6000000 is replaced with 5000000 the LED simply stays on permanently. Why is that?

Simulating with Icarus shows the expected state changes, no matter what the divisor is.


Category: fpga Time: 2016-07-30 Views: 0
Tags: fpga verilog

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