Preface: Forgive my terminology and explanation, everything I know I learned from reading on google and fiddling in spice based simulators.
I created this circuit in an app I have on my phone that runs the circuit and lets you see the output. please ignore the output as I captured this screenshot right before the app crashed my phone.
So, I went about trying to design create a NAND based SR latch which would serve as the core of my JK circuit, which I believe I accomplished by adding a second NPN transistor in series to a NOR Gated SR design. but looking at the JK flip flop diagram, it looks like I need to add two more NAND gates. I believe the gates will output to the emitters of S and R of my latch, and for each of the new NANDS they will be tied into the SR by the transistor base. I hope that is correct. However, I'm not clear on how to physically create a NAND gate with 3 inputs. I am going to create a circuit lab diagram of what I think I need to add. And I'll attach it shortly, but I wanted to see if I truly understand this.